UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 666

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

666
Interrupt request a
Interrupt request e
Interrupt request g
Interrupt request c
Caution To perform multiple interrupt servicing, the values of the EIPC and EIPSW registers must be
Remarks 1. a to u in the figure are the temporary names of interrupt request signals shown for the sake of
Figure 19-7. Example of Processing in Which Another Interrupt Request Signal Is Issued
(level 3)
(level 3)
(level 2)
(level 1)
2. The default priority in the figure indicates the relative priority between two interrupt request
saved before executing the EI instruction. When returning from multiple interrupt servicing,
restore the values of EIPC and EIPSW after executing the DI instruction.
explanation.
signals.
Main routine
EI
Interrupt request f
Interrupt request d
CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION
Interrupt request h
Interrupt
request b
(level 2)
(level 1)
(level 3)
(level 2)
While an Interrupt Is Being Serviced (1/2)
EI
EI
EI
Preliminary User’s Manual U18953EJ1V0UD
Servicing of a
Servicing of c
Servicing of d
Servicing of e
Servicing of f
Servicing of g
Servicing of h
Servicing of b
Interrupt request b is acknowledged because the
priority of b is higher than that of a and interrupts are
enabled.
Although the priority of interrupt request d is higher
than that of c, d is held pending because interrupts
are disabled.
Interrupt request f is held pending even if interrupts are
enabled because its priority is lower than that of e.
Interrupt request h is held pending even if interrupts are
enabled because its priority is the same as that of g.