UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 62

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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(3) On-chip peripheral I/O area
(4) External memory area
4 KB of addresses 03FFF000H to 03FFFFFFH are reserved as the on-chip peripheral I/O area.
Peripheral I/O registers that have functions to specify the operation mode for and monitor the status of the on-
chip peripheral I/O are mapped to the on-chip peripheral I/O area. Program cannot be fetched from this area.
Cautions 1. When a register is accessed in word units, a word area is accessed twice in halfword
15 MB (00100000H to 00FFFFFFH) are allocated as the external memory area. For details, see CHAPTER 5
BUS CONTROL FUNCTION.
Caution The V850ES/JG3-L has 22 address pins (A0 to A21), so the external memory area appears as
2. If a register that can be accessed in byte units is accessed in halfword units, the higher 8
3. Addresses not defined as registers are reserved for future expansion. The operation is
4. The internal ROM/RAM area and on-chip peripheral I/O area are assigned to successive
a repeated 4 MB image.
units in the order of lower area and higher area, with the lower 2 bits of the address
ignored.
bits are undefined when the register is read, and data is written to the lower 8 bits.
undefined and not guaranteed when these addresses are accessed.
addresses.
When accessing the internal ROM/RAM area by incrementing or decrementing addresses
using a pointer operation or such, be careful not to access the on-chip peripheral I/O area
by mistakenly extending over the internal ROM/RAM area boundary.
Physical address space
0 3 F F F F F F H
0 3 F F F 0 0 0 H
Figure 3-8. On-Chip Peripheral I/O Area
Preliminary User’s Manual U18953EJ1V0UD
CHAPTER 3 CPU FUNCTION
On-chip peripheral I/O area
(4 KB)
Logical address space
F F F F F F F F H
F F F F F 0 0 0 H