UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 365

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
(c) Generation timing of compare match interrupt request signal (INTTQ0CCk)
The timing of generation of the INTTQ0CCk signal in the PWM output mode differs from the timing of other
INTTQ0CCk signals; the INTTQ0CCk signal is generated when the count value of the 16-bit counter
matches the value of the TQ0CCRk register.
Count clock
− 2
− 1
16-bit counter
D
D
D
D
+ 1
D
+ 2
k
k
k
k
k
CCRk buffer register
D
k
TOQ0k pin output
INTTQ0CCk signal
Remark
k = 1 to 3
Usually, the INTTQ0CCk signal is generated in synchronization with the next counting up after the count
value of the 16-bit counter matches the value of the TQ0CCRk register.
In the PWM output mode, however, it is generated one clock earlier. This is because the timing is changed
to match the change timing of the output signal of the TOQ0k pin.
365
Preliminary User’s Manual U18953EJ1V0UD