UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 731

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

23.1 Functions
signal when oscillation of the main clock is stopped.
any means other than reset.
Registers to Check Reset Source.
23.2 Configuration
The clock monitor samples the main clock by using the internal oscillation clock and generates a reset request
Once the operation of the clock monitor has been enabled by an operation enable flag, it cannot be cleared to 0 by
When a reset by the clock monitor occurs, the RESF.CLMRF bit is set. For details on the RESF register, see 22.2
The clock monitor automatically stops under the following conditions.
• During oscillation stabilization time after STOP mode is released
• When the main clock is stopped (from when the PCC.MCK bit = 1 during subclock operation, until the PCC.CLS
• When the sampling clock (internal oscillation clock) is stopped
• When the CPU operates with the internal oscillation clock
The clock monitor includes the following hardware.
Control register
bit = 0 during main clock operation)
Internal oscillation clock
Item
Main clock
Figure 23-1. Timing of Reset via the RESET Pin Input
Table 23-1. Configuration of Clock Monitor
Preliminary User’s Manual U18953EJ1V0UD
CHAPTER 23 CLOCK MONITOR
Clock monitor mode register (CLM)
Clock monitor mode
register (CLM)
Enable/disable
CLME
Configuration
Internal reset signal
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