UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 273

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

TPnIOC1
TPnIOC2
TPnOPT0
(d) TMPn I/O control register 1 (TPnIOC1)
(e) TMPn I/O control register 2 (TPnIOC2)
(f) TMPn option register 0 (TPnOPT0)
(g) TMPn counter read buffer register (TPnCNT)
(h) TMPn capture/compare registers 0 and 1 (TPnCCR0 and TPnCCR1)
The value of the 16-bit counter can be read by reading the TPnCNT register.
These registers function as capture registers or compare registers depending on the setting of the
TPnOPT0.TPnCCSm bit.
When the registers function as capture registers, they store the count value of the 16-bit counter when
the valid edge input to the TIPnm pin is detected.
When the registers function as compare registers and when D
INTTPnCCm signal is generated when the counter reaches (D
TOPnm pin is inverted.
Remark
0
0
0
n = 0 to 5
m = 0, 1
Figure 7-31. Register Setting in Free-Running Timer Mode (2/2)
0
0
0
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
TPnCCS1
0
0
0/1
Preliminary User’s Manual U18953EJ1V0UD
TPnCCS0
0/1
0
0
TPnEES1
TPnIS3
0/1
0/1
0
TPnEES0 TPnETS1 TPnETS0
TPnIS2
0/1
0/1
0
TPnIS1
0/1
0
0
m
m
is set to the TPnCCRm register, the
+ 1), and the output signal of the
TPnIS0
TPnOVF
0/1
0
0/1
Select valid edge
of TIPn0 pin input
Select valid edge
of TIPn1 pin input
Select valid edge of
external event count input
Overflow flag
Specifies if TPnCCR0
register functions as
capture or compare register
Specifies if TPnCCR1
register functions as
capture or compare register
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