UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 195

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(1) Main clock oscillator
(2) Subclock oscillator
(3) Main clock oscillator stop control
(4) Internal oscillator
(5) Prescaler 1
(6) Prescaler 2
(7) Prescaler 3
(8) PLL
The main clock oscillator connects the ceramic/crystal resonator to X1 and X2 pins and oscillates the following
frequencies (f
• In clock-through mode
• In PLL mode
The external clock of the following frequency is input to the X1 pin.
• In clock-through/PLL mode
The sub-resonator oscillates a frequency of 32.768 kHz (f
This circuit generates a control signal that stops oscillation of the main clock oscillator.
Oscillation of the main clock oscillator is stopped in the STOP mode or when the PCC.MCK bit = 1 (valid only
when the PCC.CLS bit = 1).
Oscillates a frequency (f
This prescaler generates the clock (f
TMP0 to TMP5, TMQ0, TMM0, CSIB0 to CSIB4, UARTA0 to UARTA2, I
This circuit divides the main clock (f
The clock generated by prescaler 2 (f
(f
f
This circuit divides the clock generated by the main clock oscillator (f
and supplies that clock to the watch timer block.
For details, see CHAPTER 10 WATCH TIMER FUNCTIONS.
This circuit multiplies the clock generated by the main clock oscillator (f
It operates in two modes: clock-through mode in which f
clock is output. These modes can be selected by using the PLLCTL.SELPLL bit.
Whether the clock is multiplied by 4 is selected by the CKC.CKDIV0 bit, and PLL is started or stopped by the
PLLCTL.PLLON bit.
CLK
CPU
f
f
f
X
X
X
is the clock supplied to the INTC, ROM, RAM, and DMA blocks, and can be output from the CLKOUT pin.
) and internal system clock (f
= 2.5 to 10 MHz
= 2.5 to 5 MHz
= 2.5 to 5 MHz
X
).
R
) of 220 kHz (TYP.).
CHAPTER 6 CLOCK GENERATION FUNCTION
CLK
Preliminary User’s Manual U18953EJ1V0UD
XX
).
XX
).
to f
XX
to f
XX
/1,024) to be supplied to the following on-chip peripheral functions:
XX
/32) is supplied to the selector that generates the CPU clock
X
XT
is output as is, and PLL mode in which a multiplied
).
X
X
2
) by 4.
) to a specific frequency (32.768 kHz)
C00 to I
2
C02, ADC, DAC, and WDT2
195