UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 484

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

15.6.5 UART transmission
by writing transmit data to the UAnTX register. The start bit, parity bit, and stop bit are automatically added.
enabled at the transmit destination.
operation.
of the UAnTX register to the UARTAn transmit shift register, and thereafter the contents of the UARTAn transmit shift
register are output to the TXDAn pin.
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A high level is output to the TXDAn pin by setting the UAnCTL0.UAnPWR bit to 1.
Next, the transmission enabled status is set by setting the UAnCTL0.UAnTXE bit to 1, and transmission is started
Since the CTS (transmit enable signal) input pin is not provided in UARTAn, use a port to check that reception is
The data in the UAnTX register is transferred to the UARTAn transmit shift register upon the start of the transmit
A transmission enable interrupt request signal (INTUAnT) is generated upon completion of transmission of the data
Write of the next transmit data to the UAnTX register is enabled after the INTUAnT signal is generated.
Remark
TXDAn
INTUAnT
LSB first
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
Start
bit
D0
Figure 15-10. UART Transmission
Preliminary User’s Manual U18953EJ1V0UD
D1
D2
D3
D4
D5
D6
D7
Parity
bit
Stop
bit