UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 730

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

22.4 Cautions
when the reset status is released. The usable range of the supply voltage of the V850ES/JG3-L differs depending on
the internal operating frequency (2.2 to 2.7 V @5 MHz (MAX.) or 2.7 to 3.6 V @20 MHz (MAX.)). Therefore, observe
the following points.
730
When executing the power-on reset operation, the supply voltage must be within the guaranteed operating range
(1) At less than 2.2 V when reset is released
(2) At 2.2 V or more to less than 2.7 V when reset is released
(3) At 2.7 to 3.6 V when reset is released
Use prohibited
• Input f
• Inputting 5 MHz or more to the main clock oscillator is prohibited.
• Be sure to stop PLL (PLLCTL.PLLON = 0) by the initialization routine.
• Both the clock through mode and PLL mode can be used.
Remarks 1. The voltage value (V) is the value of V
X
= 2.5 to 5 MHz to the main clock oscillator and set the clock through mode (PLLCTL.SELPLL = 0).
2. The reset status is released in the following timing. For the relationship between the rising of
V
SPECIFICATIONS (TARGET).
DD
and releasing the reset status by the RESET pin, see CHAPTER 30
RESET
V
DD
Preliminary User’s Manual U18953EJ1V0UD
CHAPTER 22 RESET FUNCTIONS
DD
.
Reset release
ELECTRICAL