UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 637

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(6) DMA trigger factor registers 0 to 3 (DTFR0 to DTFR3)
Note Write 0 to this bit to clear a DMA transfer request if an interrupt that is specified as the cause of starting
Cautions 1. Set the IFCn5 to IFCn0 bits at the following timing when DMA transfer is disabled
Remark
The DTFR0 to DTFR3 registers are 8-bit registers that control the DMA transfer start trigger via interrupt
request signals from on-chip peripheral I/O.
The interrupt request signals set by these registers serve as DMA transfer start factors.
These registers can be read or written in 8-bit units. However, DFn bit can be read or written in 1-bit units.
Reset sets these registers to 00H.
DMA transfer occurs while DMA transfer is disabled.
2. An interrupt request that is generated in the standby mode (IDEL1, IDLE2, STOP, or sub-
3. If a DMA start factor is selected by the IFCn5 to IFCn0 bits, the DFn bit is set to 1 when an
For the IFCn5 to IFCn0 bits, see Table 18-1 DMA Start Factors.
(n = 0 to 3)
(DCHCn.Enn bit = 0).
IDLE mode) does not start the DMA transfer cycle (nor is the DFn bit set to 1).
interrupt occurs from the selected on-chip peripheral I/O, regardless of whether the DMA
transfer is enabled or disabled.
immediately started.
• Period from after reset to start of first DMA transfer
• Period from after channel initialization by DCHCn.INITn bit to start of DMA transfer
• Period from after completion of DMA transfer (DCHCn.TCn bit = 1) to start of the next
DTFRn
After reset:
DMA transfer
DFn
00H
DFn
<7>
0
1
Note
CHAPTER 18 DMA FUNCTION (DMA CONTROLLER)
No DMA transfer request
DMA transfer request
R/W
0
6
Preliminary User’s Manual U18953EJ1V0UD
Address:
IFCn5
5
DTFR0 FFFFF810H, DTFR1 FFFFF812H,
DTFR2 FFFFF814H, DTFR3 FFFFF816H
DMA transfer request status flag
If DMA is enabled in this status, DMA transfer is
IFCn4
4
IFCn3
3
IFCn2
2
IFCn1
1
IFCn0
0
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