UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 225

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

TPnIOC0
(c) TMPn I/O control register 0 (TPnIOC0)
(d) TMPn counter read buffer register (TPnCNT)
(e) TMPn capture/compare register 0 (TPnCCR0)
(f) TMPn capture/compare register 1 (TPnCCR1)
By reading the TPnCNT register, the count value of the 16-bit counter can be read.
If the TPnCCR0 register is set to D
Interval = (D
Usually, the TPnCCR1 register is not used in the interval timer mode. However, the set value of the
TPnCCR1 register is transferred to the CCR1 buffer register. A compare match interrupt request signal
(INTTPnCC1) is generated when the count value of the 16-bit counter matches the value of the CCR1
buffer register.
Therefore, mask the interrupt request by using the corresponding interrupt mask flag (TPnCCMK1).
Remarks 1. TMPn I/O control register 1 (TPnIOC1), TMPn I/O control register 2 (TPnIOC2), and TMPn
0
2. n = 0 to 5
Figure 7-4. Register Setting for Interval Timer Mode Operation (2/2)
0
0
+ 1) × Count clock cycle
option register 0 (TPnOPT0) are not used in the interval timer mode.
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
0
Preliminary User’s Manual U18953EJ1V0UD
0
0
, the interval is as follows.
TPnOL1
0/1
TPnOE1 TPnOL0
0/1
0/1
TPnOE0
0/1
0: Disable TOPn0 pin output
1: Enable TOPn0 pin output
Setting of output level with
operation of TOPn0 pin disabled
0: Low level
1: High level
0: Disable TOPn1 pin output
1: Enable TOPn1 pin output
Setting of output level with
operation of TOPn1 pin disabled
0: Low level
1: High level
225