UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 725

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UPD70F3737GC-UEU-AX

Manufacturer Part Number
UPD70F3737GC-UEU-AX
Description
MCU 32BIT V850ES/JX3-L 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet

Specifications of UPD70F3737GC-UEU-AX

Package / Case
*
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Speed
20MHz
Number Of I /o
84
Core Processor
RISC
Program Memory Type
FLASH
Ram Size
8K x 8
Program Memory Size
128KB (128K x 8)
Data Converters
A/D 12x10b, D/A 2x8b
Oscillator Type
Internal
Peripherals
DMA, LVD, PWM, WDT
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Core Size
32-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3737GC-UEU-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
22.3.2 Reset operation by watchdog timer 2
(WDT2RES signal generation), a system reset is executed and the hardware is initialized to the initial status.
and the reset status is then automatically released.
Main clock oscillator (f
Subclock oscillator (f
Internal oscillator
Peripheral clock (f
Internal system clock (f
CPU clock (f
CPU
Watchdog timer 2
Internal RAM
I/O lines (ports/alternate-function
pins)
On-chip peripheral I/O register
On-chip peripheral functions other
than above
When watchdog timer 2 is set to the reset operation mode due to overflow, upon watchdog timer 2 overflow
Following watchdog timer 2 overflow, the reset status is entered and lasts the predetermined time (analog delay),
The main clock oscillator is stopped during the reset period.
CPU
)
Item
XX
to f
XT
X
Table 22-2. Hardware Status During Watchdog Timer 2 Reset Operation
)
)
XX
XX
),
/1,024)
Oscillation stops
Oscillation continues
Oscillation stops
Operation stops
Operation stops
Initialized
Operation stops (initialized to 0)
Undefined if power-on reset or CPU access and reset input conflict (data is damaged).
Otherwise value immediately after reset input is retained.
High impedance
Operation stops
Initialized to specified status, OCDM register retains its value.
Preliminary User’s Manual U18953EJ1V0UD
CHAPTER 22 RESET FUNCTIONS
During Reset
Oscillation starts
Oscillation starts
Operation starts after securing oscillation
stabilization time
Operation starts after securing oscillation
stabilization time (initialized to f
Program execution after securing
oscillation stabilization time
Counts up from 0 with internal oscillation
clock as source clock.
Operation can be started after securing
oscillation stabilization time.
After Reset
XX
/8)
725

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