UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 613

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

17.14.2 When communication reservation function is disabled (IICFn.IICRSVn bit = 1)
request is rejected and a start condition is not generated. There are two modes in which the bus is not used
time shown in Table 17-7 is required until the STCFn flag is set after setting the STTn bit to 1. Therefore, secure the
time by software.
When the IICCn.STTn bit is set when the bus is not used in a communication during bus communication, this
• When arbitration results in neither master nor slave operation
• When an extension code is received and slave operation is disabled (ACK is not returned and the bus was
To confirm whether the start condition was generated or request was rejected, check the IICFn.STCFn flag. The
released when the IICCn.LRELn bit was set to 1) (n = 0 to 2).
OCKSENm
Remarks 1. ×: don’t care
1
1
1
1
0
2. n = 0 to 2
OCKSm1
m = 0, 1
0
0
1
1
0
Preliminary User’s Manual U18953EJ1V0UD
OCKSm0
Table 17-7. Wait Periods
CHAPTER 17 I
0
1
0
1
0
CLn1
0
0
0
0
1
2
C BUS
CLn0
×
×
×
×
0
Wait Period
10 clocks
15 clocks
20 clocks
25 clocks
5 clocks
613