UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 681

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(2) Restoration
Restoration from a debug trap is executed with the DBRET instruction.
With the DBRET instruction, the CPU performs the following steps and transfers control to the address of the
restored PC.
<1> The restored PC and PSW are read from DBPC and DBPSW.
<2> Control is transferred to the fetched address of the restored PC and PSW.
Caution DBPC and DBPSW can be accessed only during the interval between the execution of the
The processing format for restoration from a debug trap is shown below.
DBTRAP instruction and DBRET instruction.
Figure 19-14. Processing Format of Restoration from Debug Trap
CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION
Preliminary User’s Manual U18953EJ1V0UD
Jump to address of restored PC
PC
PSW
DBRET instruction
DBPC
DBPSW
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