UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 550

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16.9 Cautions
550
(1)
(2)
(3) In communication type 2 or 4 (CBnCTL1.CBnDAP bit = 1), the CBnSTR.CBnTSF bit is cleared half a SCKBn
Remark
clock after occurrence of a reception complete interrupt (INTCBnR).
In the single transfer mode, writing the next transmit data is ignored during communication (CBnTSF bit = 1),
and the next communication is not started. Also if reception-only communication (CBnCTL0.CBnTXE bit = 0,
CBnCTL0.CBnRXE bit = 1) is set, the next communication is not started even if the receive data is read during
communication (CBnTSF bit = 1).
Therefore, when using the single transfer mode with communication type 2 or 4 (CBnDAP bit = 1), pay
particular attention to the following.
• To start the next transmission, confirm that CBnTSF bit = 0 and then write the transmit data to the CBnTX
• To perform the next reception continuously when reception-only communication (CBnTXE bit = 0, CBnRXE
Or, use the continuous transfer mode instead of the single transfer mode. Use of the continuous transfer mode
is recommended especially for using DMA.
In regards to registers that are forbidden from being rewritten during operations (CBnCTL0.CBnPWR bit is 1),
When transferring transmit data and receive data using DMA transfer, error processing cannot be performed
even if an overrun error occurs during serial transfer. Check that the no overrun error has occurred by
reading the CBnSTR.CBnOVE bit after DMA transfer has been completed.
if rewriting has been carried out by mistake during operations, set the CBnCTL0.CBnPWR bit to 0 once, then
initialize CSIBn.
Registers to which rewriting during operation are prohibited are shown below.
• CBnCTL0 register: CBnTXE, CBnRXE, CBnDIR, CBnTMS bits
• CBnCTL1 register: CBnCKP, CBnDAP, CBnCKS2 to CBnCKS0 bits
• CBnCTL2 register: CBnCL3 to CBnCL0 bits
register.
bit = 1) is set, confirm that CBnTSF bit = 0 and then read the CBnRX register.
n = 0 to 4
CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB)
Preliminary User’s Manual U18953EJ1V0UD