UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 199

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(b) Example of setting subclock operation → main clock operation
<1> MCK bit ← 0:
<2> Insert waits by the program and wait until the oscillation stabilization time of the main clock elapses.
<3> CK3 bit ← 0:
<4> Main clock operation:
Caution Enable operation of the on-chip peripheral functions operating with the main clock only
[Description example]
<1> _START_MAIN_OSC :
<2> movea
<3> st.b
<4> _CHECK_CLS :
Remark The description above is simply an example. Note that in <4> above, the CLS bit is read in a
_DMA_DISABLE:
clrl
st.b
clr1
_WAIT_OST :
nop
nop
nop
addi
cmp
bne
clr1
tst1
bnz
_DMA_ENABLE:
setl
after the oscillation of the main clock stabilizes. If their operations are enabled before
the lapse of the oscillation stabilization time, a malfunction may occur.
closed loop.
0, DCHCn[r0]
r0, PRCMD[r0]
6, PCC[r0]
0x55, r0, r11
-1, r11, r11
r0, r11
r0, PRCMD[r0]
3, PCC[r0]
4, PCC[r0]
_CHECK_CLS
0, DCHCn[r0]
CHAPTER 6 CLOCK GENERATION FUNCTION
Preliminary User’s Manual U18953EJ1V0UD
Main clock starts oscillating
Use of a bit manipulation instruction is recommended. Do not change the
CK2 to CK0 bits.
It takes the following time after the CK3 bit is set until main clock operation
is started.
Therefore, insert one NOP instruction immediately after setting the CK3 bit
to 0 or read the CLS bit to check if main clock operation has started.
_WAIT_OST
Max.: 1/f
XT
(1/subclock frequency)
-- DMA operation disabled. n = 0 to 3
-- Release of protection of special registers
-- Main clock starts oscillating.
-- Wait for oscillation stabilization time.
-- CK3 ← 0
-- Wait until main clock operation starts.
-- DMA operation enabled. n = 0 to 3
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