UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 716

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

21.7.2 Releasing subclock operation mode
voltage detector (LVI), or clock monitor (CLM)) when the CK3 bit is set to 0.
clock by software, and set the CK3 bit to 0.
21.7.3 Releasing low-voltage subclock operation mode
that, transit to the normal mode according to 21.7.2 Releasing subclock operation mode. Be sure to follow this
procedure to transit the mode from the low-voltage subclock operation mode to the subclock operation mode.
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The subclock operation mode is released by a reset signal (reset by RESET pin input, WDT2RES signal, low-
If the main clock is stopped (MCK bit = 1), set the MCK bit to 1, secure the oscillation stabilization time of the main
The normal operation mode is restored when the subclock operation mode is released.
Caution When manipulating the CK3 bit, do not change the set values of the CK2 to CK0 bits (using a bit
In low-voltage subclock mode, the subclock operation mode is set by setting the REGOVL0 register to 00H. After
(1) Procedure for setting “low-voltage subclock operation mode” → “subclock operation mode”
(2) If low-voltage subclock operation mode is released by reset
Make the following settings in the low-voltage subclock operation mode.
<1> • Disable the maskable interrupt by the DI instruction.
<2> Write C9H (enabling data) to the REGPR register.
<3> Write 00H to the REGOVL0 register (transit to the subclock operation mode).
<4> Write 00H (protection data) to the REGPR register.
<5> Wait for at least 800
<6> As necessary, enable the maskable interrupt, NMI interrupt, or INTWDT2 interrupt by the EI instruction
<7> Enable the DMA if necessary.
<8> Start the functions to be used, from among those that have been stopped in steps <1> and <2> in
Be sure to observe the above sequence.
Note, however, that <6>, <7>, and <8> may be performed at any time as long as it is done after <5>.
When the low-voltage subclock operation mode is released by a reset signal (reset by RESET pin input,
WDT2RES signal, low-voltage detector (LVI), or clock monitor (CLM)), the CPU transits to the normal operation
mode after it has been released from the reset status, and the REGOVL0 register is initialized to 00H and the
REGPR register to 00H (protection data). Make sure by setting an option byte that the time necessary for
setting up the regulator elapses.
• Disable the NMI interrupt (INTF02 = 0, INTR02 = 0).
• Create a status in which the INTWDT2 signal is not generated (stop watchdog timer 2 or set a mode
(restore the setting <1> above).
section 21.7.1 (1) Procedure for setting “subclock operation mode” → “low-voltage subclock
operation mode”.
manipulation instruction to manipulate the bit is recommended).
For details of the PCC register, see 6.3 (1) Processor clock control register (PCC).
other than the INTWDT2 mode. Create a status in which the INTWDT2 signal is not generated
immediately after watchdog timer 2 has been cleared).
μ
s by software.
CHAPTER 21 STANDBY FUNCTION
Preliminary User’s Manual U18953EJ1V0UD
For details, see CHAPTER 27 OPTION BYTE.