UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 28

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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(10) Watchdog timer 2
(11) Serial interface
(12) A/D converter
(13) D/A converter
(14) DMA controller
(15) Key interrupt function
(16) Real-time output function
(17) CRC function
(18) DCU (debug control unit)
A watchdog timer is provided on chip to detect inadvertent program loops, system abnormalities, etc.
The internal oscillation clock, the main clock, or the subclock can be selected as the source clock.
Watchdog timer 2 generates a non-maskable interrupt request signal (INTWDT2) or a system reset signal
(WDT2RES) after an overflow occurs.
The V850ES/JG3-L includes three kinds of serial interfaces: asynchronous serial interface A (UARTA), 3-wire
variable-length serial interface B (CSIB), and an I
In the case of UARTA, data is transferred via the TXDA0 to TXDA2 pins and RXDA0 to RXDA2 pins.
In the case of CSIB, data is transferred via the SOB0 to SOB4 pins, SIB0 to SIB4 pins, and SCKB0 to
SCKB4 pins.
In the case of I
This 10-bit A/D converter includes 12 analog input pins. Conversion is performed using the successive
approximation method.
A two-channel, 8-bit-resolution D/A converter that uses the R-2R ladder method is provided on chip.
A 4-channel DMA controller is provided on chip. This controller transfers data between the internal RAM and
on-chip peripheral I/O devices in response to interrupt requests sent by on-chip peripheral I/O.
A key interrupt request signal (INTKR) can be generated by inputting a falling edge to the key input pins (8
channels).
The real-time output function transfers preset 6-bit data to output latches upon the occurrence of a timer
compare register match signal.
A CRC operation circuit that generates a 16-bit CRC (Cyclic Redundancy Check) code upon setting of 8-bit
data is provided on-chip.
An on-chip debug function that uses the JTAG (Joint Test Action Group) communication specifications is
provided. Switching between the normal port function and on-chip debugging function is done with the
control pin input level and the OCDM register.
2
C, data is transferred via the SDA00 to SDA02 and SCL00 to SCL02 pins.
Preliminary User’s Manual U18953EJ1V0UD
CHAPTER 1 INTRODUCTION
2
C bus interface (I
2
C).