EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 1005

• Manufacturer Part Number: EP4SE530H35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 744
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Protocol Settings
Table 1–14. MegaWizard Plug-In Manager Options (Protocol Settings —GIGE and XAUI) (Part 1 of 3)
February 2011 Altera Corporation
Enable run-length violation
checking with a run length of __.
Create an rx_syncstatus output
port for pattern detector and word
aligner.
Create an rx_patterndetect port
to indicate pattern detected.
Create an rx_invpolarity port to
enable word aligner polarity
inversion.
Create an rx_ctrldetect port to
indicate 8B/10B decoder has
detected a control code.
Create an rx_errdetect port to
indicate 8B/10B decoder has
detected an error code.
ALTGX Setting
Table 1–14
Settings screen of the MegaWizard Plug-In Manager for your ALTGX custom
megafunction variation.
lists the available options for the GIGE and XAUI modes in the Protocol
This option creates the output signal rx_rlv.
Enabling this option also activates the run-length
violation circuit. If the number of continuous 1s
and 0s exceeds the number that you set in this
option, the run-length violation circuit asserts the
rx_rlv signal. The rx_rlv signal is
asynchronous to the receiver data path and is
asserted for a minimum of two recovered clock
cycles.
The run length limits are five to 160 in increments
of five.
This is an output status signal that the word
aligner forwards to the FPGA fabric to indicate
that synchronization has been achieved. This
signal is synchronous with the parallel receiver
data on the rx_dataout port. Receiver
synchronization is indicated on the
rx_syncstatus port of each channel.
This is an output status signal that the word
aligner forwards to the FPGA fabric to indicate
that the word alignment pattern programmed has
been detected in the current word boundary.
This optional port allows you to dynamically
reverse the polarity of every bit of the received
data at the input of the word aligner. Use this
option when the positive and negative signals of
the differential input to the receiver (rx_datain)
are erroneously swapped on the board.
This is an output status signal that the 8B/10B
decoder forwards to the FPGA fabric. This signal
indicates whether the decoded 8-bit code group is
a data or control code group on this port. If the
received 10-bit code group is one of the 12
control code groups (/Kx.y/) specified in
IEEE802.3 specification, this signal is driven high.
If the received 10-bit code group is a data code
group (/Dx.y/), this signal is driven low.
This is an output status signal that the 8B/10B
decoder forwards to the FPGA fabric. This signal
indicates an 8B/10B code group violation. It is
asserted high if the received 10-bit code group
has a code violation or disparity error. It is used
along with the rx_disperr signal to differentiate
between a code violation error and/or a disparity
error.
Description
“Programmable Run Length
Violation Detection” section in
the
Stratix IV Devices
Table 1-33 and the “Word
Aligner” section in the
Transceiver Architecture in
Stratix IV Devices
Table 1-33 and the “Word
Aligner” section in the
Transceiver Architecture in
Stratix IV Devices
“Receiver Polarity Inversion”
section in the
Architecture in Stratix IV Devices
chapter.
“8B/10B Decoder” section in the
Transceiver Architecture in
Stratix IV Devices Chapter
chapter.
“8B/10B Decoder” section in the
Transceiver Architecture in
Stratix IV Devices
Stratix IV Device Handbook Volume 3
Transceiver Architecture in
Reference
Transceiver
chapter.
chapter.
chapter.
chapter.
1–47