EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 590

• Manufacturer Part Number: EP4SE530H35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 744
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

1–146
Figure 1–116. Dynamic Switch Signaling in PCIe ×4 Mode
Table 1–55. Transceiver Clock Frequencies Signaling Rates in PCIe ×4 Mode (Part 1 of 2)
Stratix IV Device Handbook Volume 2: Transceivers
High-Speed Serial Clock
Low-Speed Parallel Clock
Serial Recovered Clock
FPGA
Fabric
Transceiver Clocks
Interface
rateswitch
PIPE
Figure 1–116
(5 Gbps) data rate.
In PCIe ×4 mode configured at Gen2 (5 Gbps) data rate, when the PCIe rateswitch
controller sees a transition on the rateswitch signal, it sends the pcie_gen2switch
control signal to the PCIe clock switch circuitry in the CMU0 clock divider block and the
receiver CDR to switch to the instructed signaling rate. A low-to-high transition on
the rateswitch signal initiates a Gen1 (2.5 Gbps) to Gen2 (5 Gbps) signaling
rateswitch. A high-to-low transition on the rateswitch signal initiates a Gen2
(5 Gbps) to Gen1 (2.5 Gbps) signaling rateswitch.
Table 1–55
2.5 Gbps and 5 Gbps signaling rates.
reset_int
reset_int
Compensation
Compensation
Transceiver
Transmitter
Controller
Receiver
Express
Phase
Phase
Switch
FIFO
FIFO
PCS
Rate
PCI
Dynamic Switch Between Gen1 (2.5 Gbps) and Gen2 (5 Gbps) Signaling Rates in PCIe
×4 Mode
CCU
lists the transceiver clock frequencies when switching between the
Gen1 (2.5 Gbps) to Gen2 (5 Gbps) Switch
shows the PCIe rateswitch circuitry in PCIe ×4 mode configured at Gen2
rx_locktorefclk
rx_freqlocked
rx_locktodata
signal detect
(Low-to-High Transition on the
rx_datain
rx_cruclk
CMU0
CMU1
PLL
PLL
250 MHz to 500 MHz
1.25 GHz to 2.5 GHz
1.25 GHz to 2.5 GHz
rateswitch Signal)
/1, /2, /4
pcie_gen2switch_done
/2
pcie_gen2switch
Frequency
Controller
LTR/LTD
Detector
Detector
Phase
Phase
(PD)
(PD)
Clock and Data Recovery (CDR) Unit
/1, /2, /4
CMU0 Clock Divider
CMU1 Clock Divider
/1, /2, /4
pcie_gen2switch
Chapter 1: Transceiver Architecture in Stratix IV Devices
Clock Switch
PCI Express
Circuitry
Loop Filter
Pump +
Charge
Gen2 (5 Gbps) to Gen1 (2.5 Gbps) Switch
1
0
/4, /5, /8, /10
(High-to-Low Transition on the
V
/M
CO
CMU0_Channel
CMU1_Channel
/2
/4, /5, /8, /10
500 MHz to 250 MHz
2.5 GHz to 1.25 GHz
2.5 GHz to 1.25 GHz
rateswitch Signal)
February 2011 Altera Corporation
PCI Express Clock Switch Circuitry
/L
Transceiver Block Architecture
Transceiver Block
Low-Speed Parallel
High-Speed Serial
(PIPE x4) Bonded
Bonded Channels
Clock to the Four
Recovered
Recovered
Four (PIPE x4)
Parallel
Serial
Clock to the
Clock
Clock
Channels