EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 246

• Manufacturer Part Number: EP4SE530H35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 744
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

7–26
Stratix IV Device Handbook Volume 1
Using the R
Combining ×16/×18 DQS/DQ Groups for a ×36 QDR II+/QDR II SRAM Interface
f
1
1
You can use the DQS/DQSn pins in some of the ×4 groups as R
in the pin table). You cannot use a ×4 DQS/DQ group for memory interfaces if any of
its pin members are used as R
use the ×8/×9 group that includes this ×4 DQS/DQ group, if either of the following
applies:
■
■
You can use the ×8/×9 group because a DQS/DQ ×8/×9 group actually comprises 12
pins, as the groups are formed by stitching two DQS/DQ groups in ×4 mode with six
pins each (refer to
one DQS, one DM, and eight DQ pins that add up to 10 pins. If you choose your pin
assignment carefully, you can use the two extra pins for R
SDRAM interface, you must use differential DQS, which means that you only have
one extra pin. In this case, pick different pin locations for the R
example, in the bank that contains the address and command pins).
You cannot use the R
×9 QDR II+/QDR II SRAM devices, as the R
the CQn pins. In this case, pick different pin locations for R
conflict with memory interface pin placement. In this case, you have the choice of
placing the R
address and command pins.
There is no restriction on using ×16/×18 or ×32/×36 DQS/DQ groups that include the
×4 groups whose pins are being used as R
extra pins that can be used as DQS pins.
For ×8, ×16/×18, or ×32/×36 DQS/DQ groups whose members are used for R
R
not be able to place DQS and DQ pins without manual pin assignments, resulting in a
“no-fit”.
This implementation combines ×16/×18 DQS/DQ groups to interface with a ×36
QDR II+/QDR II SRAM device. The ×36 read data bus uses two ×16/×18 groups
while the ×36 write data uses another two ×16/×18 or four ×8/×9 groups. The
CQ/CQn signal traces are split on the board trace to connect to two pairs of CQ/CQn
pins in the FPGA. This is the only connection on the board that you need to change for
this implementation. Other QDR II+/QDR II SRAM interface rules for Stratix IV
devices also apply for this implementation.
The ALTMEMPHY megafunction and UniPHY-based external memory interface IPs
do not use the QVLD signal, so you can leave the QVLD signal unconnected as in any
QDR II+/QDR II SRAM interface.
For more information about the ALTMEMPHY megafunction or UniPHY-based IPs,
refer to the
DN
UP
You are not using DM pins with your differential DQS pins
You are not using complementary or differential DQS pins
, you must assign DQS and DQ pins manually. The Quartus
and R
External Memory Interface
UP
DN
and R
Pins in a DQS/DQ Group Used for Memory Interfaces
Table 7–1 on page
UP
DN
and R
pins in the data-write group or in the same bank as the
UP
DN
and R
pins shared with DQS/DQ group pins when using
7–5). A typical ×8 memory interface consists of
Handbook.
DN
Chapter 7: External Memory Interfaces in Stratix IV Devices
pins for OCT calibration. You may be able to
UP
UP
and R
and R
DN
DN
pins, because there are enough
pins are dual purpose with
UP
UP
and R
February 2011 Altera Corporation
and R
UP
UP
Memory Interfaces Pin Support
®
and R
and R
II software might
DN
DN
. In a DDR3
pins to avoid
DN
DN
pins (listed
pins (for
UP
and