EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 1027

• Manufacturer Part Number: EP4SE530H35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 744
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 2: Transceiver Design Flow Guide for Stratix IV Devices
Implementation and Integration
February 2011 Altera Corporation
Integrate the Design
1
Gear Boxing Logic
Some protocols require a wider data path than provided by the transceiver interface;
for example, the Interlaken Protocol requires 64/67-bit encoding and decoding, but
the maximum data path interface in the Stratix IV GX transceiver is 40 bits. Therefore,
you must implement gear box logic to interface the 64/67-bit encoder-decoder with
the transceiver interface.
Functional Blocks to Interface with the Transceiver Configured in Basic (PMA Direct) Mode
In Basic (PMA direct) mode, all the PCS functional blocks in the transceiver channel
are disabled. Therefore, you may need to implement the following blocks in the FPGA
fabric:
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After you implement all of the required logic, integrate the transceiver instances with
the remaining logic and provide the appropriate transceiver-FPGA fabric interface
clocking. Synthesize the design using third-party synthesis tools, such as Synopsys
Synplicity or the Quartus II software synthesis tool. This allows you to detect syntax
errors in your design.
If you are using the transceiver in Basic (PMA direct) mode, you must develop all the
PCS functionality in the FPGA fabric.
Word Alignment—To align the byte boundary on the received data.
Byte Deserializer—To increase the data path width to the rest of the user logic and
to reduce the clock frequency of the data path by two.
Phase Compensation FIFO (for bonded channel applications)—In bonded channel
applications in which multiple transceiver channels are connected to the same
upstream system (for example, one Interlaken Protocol link using 24 transceiver
channels). To minimize the global clock routing resources you use, implement a
phase compensation FIFO to interface the receiver side of the transceiver interface
with the logic in the FPGA Fabric.
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With this method, you only use one clock resource and the subsequent
receive-side logic in the FPGA fabric can operate in this single clock domain.
Deskew Logic (for bonded channel applications)—In bonded channel applications
in which multiple transceiver channels are connected to the same upstream
system, the data received between multiple channels are not aligned due to
potential skew in the interconnect and the upstream transmitter system. To
compensate for the skew, use deskew logic in the FPGA fabric.
Encoding/Decoding or Scrambling/Descrambling—Many protocols require the
transmitter data to be encoded or scrambled to maintain signal integrity. This logic
may be required in the FPGA fabric based on your application requirements.
Use the recovered clock from each channel to clock the write side of the phase
compensation FIFO.
Use the recovered clock from any of the channels to clock the read side of the
phase compensation FIFO.
Stratix IV Device Handbook Volume 3
2–9