EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 196

• Manufacturer Part Number: EP4SE530H35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 744
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

6–24
Table 6–5. Stratix IV MultiVolt I/O Support
On-Chip Termination Support and I/O Termination Schemes
Stratix IV Device Handbook Volume 1
1.2
1.5
1.8
2.5
3.0
Notes to
(1) The pin current may be slightly higher than the default value. You must verify that the driving device’s V
(2) Altera recommends that you use an external clamping diode on the I/O pins when the input signal is 3.0 V or 3.3 V. You have the option to use
(3) Each I/O bank of a Stratix IV device has its own VCCIO pins and supports only one V
V
CCIO
do not violate the applicable Stratix IV V
an internal clamping diode for column I/O pins.
is not supported when V
operations are only supported when V
(V)
Table
(3)
6–5:
f
1
1.2
v
—
—
—
—
For more information about pin connection guidelines, refer to the
Stratix IV E Device Family Pin Connection
The Stratix IV VCCPD power pins must be connected to a 2.5- or 3.0-V power supply.
Using these power pins to supply the pre-driver power to the output buffers increases
the performance of the output pins.
Stratix IV devices feature dynamic series and parallel OCT to provide I/O impedance
matching and termination capabilities. OCT maintains signal quality, saves board
space, and reduces external component costs.
Stratix IV devices support:
■
■
■
■
■
■
Stratix IV devices support OCT in all I/O banks by selecting one of the OCT I/O
standards.
These devices also support OCT R
standards if they use the same V
each I/O in an I/O bank to support OCT R
R
You cannot configure both OCT R
I/O buffer.
T
CCIO
.
1.5
v
v
—
—
—
On-chip series termination (R
On-chip series termination (R
On-chip Parallel termination (R
Dynamic series termination for single-ended I/O standards
Dynamic Parallel termination for single-ended I/O standards
On-chip differential termination (R
is 3.0 V. The LVDS input operations are supported when V
Input Signal (V)
1.8
v
v
—
—
—
CCIO
IL
maximum and V
is 2.5 V.
2.5
v
v
—
—
—
(Note 1)
v
IH
3.0
v
—
—
—
minimum voltage specifications.
(2)
CCIO
v
S
S
3.3
) with calibration
) without calibration
v
S
—
—
—
S
T
(2)
and programmable current strength for the same
) with calibration
and R
Table 6–5
supply voltage. You can independently configure
D
) for differential LVDS I/O standards
Guidelines.
1.2
T
v
—
—
—
—
On-Chip Termination Support and I/O Termination Schemes
in the same I/O bank for different I/O
S
, programmable current strength, or OCT
CCIO
CCIO
lists Stratix IV MultiVolt I/O support.
, either 1.2, 1.5, 1.8, or 3.0 V. The LVDS I/O standard
is 1.2 V, 1.5 V, 1.8 V, or 2.5 V. The LVDS output
1.5
—
v
—
—
—
Chapter 6: I/O Features in Stratix IV Devices
Output Signal (V)
OL
1.8
v
—
—
—
—
maximum and V
February 2011 Altera Corporation
2.5
v
—
—
—
—
Stratix IV GX and
OH
minimum voltages
3.0
v
—
—
—
—
3.3
—
—
—
—
—