EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 1052

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EP4SE530H35C2N

Manufacturer Part Number
EP4SE530H35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
STRATIX® IV Er

Specifications of EP4SE530H35C2N

Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
744
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

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2–34
Stratix IV Device Handbook Volume 3
Create Reset Logic to Control the FPGA Fabric and Transceivers
The design requires independent control on each channel. Altera recommends
creating independent reset control logic for each channel.
In this design, channel 0 and channel 2 share the same CMU PLL (because they are
configured at the same data rate) and channel 1 uses the second CMU PLL. When you
create a Transmitter Only or Receiver and Transmitter instance, the ALTGX
MegaWizard Plug-In Manager provides a pll_powerdown signal to reset the
CMU PLL that provides clocks to the transmitter channel. In this design example,
because channels 0 and 2 share the same CMU PLL, drive the pll_powerdown port of
channel 0 and channel 2 in the ALTGX instance from the same logic.
Chapter 2: Transceiver Design Flow Guide for Stratix IV Devices
Example 1: Fibre Channel Protocol Application
February 2011 Altera Corporation

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