EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 872

• Manufacturer Part Number: EP4SE530H35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 744
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

5–26
Figure 5–14. Channel and CMU PLL Reconfiguration in a Transceiver Block
Stratix IV Device Handbook Volume 2: Transceivers
refclk0
refclk1
1
Blocks that can be reconfigured in Channel and CMU PLL
Figure 5–14
channel and CMU PLL reconfiguration mode.
Channel reconfiguration from either a Transmitter only configuration to a Receiver
only configuration or vice versa is not allowed.
ALTGX MegaWizard Plug-In Manager Setup for Channel and CMU PLL Reconfiguration Mode
To reconfigure the transceiver channel and CMU PLL, set up the ALTGX MegaWizard
Plug-In Manager using the following steps:
1. Select the Channel and Transmitter PLL reconfiguration option in the Modes
2. If you want to reconfigure the data rate of the transceiver channel by reconfiguring
3. If you want to reconfigure the data rate of the transceiver channel by switching to
4. Provide the number of input reference clocks available for the CMU PLL in the
screen under the Reconfiguration Settings tab.
the CMU PLL, provide the new data rate you want the CMU PLL to run at in the
General screen.
the alternate CMU PLL within the same transceiver block, select the Use alternate
CMU transmitter PLL option in the Modes screen. For more information, refer to
the
How many input clocks? option of the corresponding PLL screen. The maximum
number of input reference clocks allowed is 10. For more information, refer to
“Guidelines for Specifying the Input Reference Clocks” on page
Reconfiguration mode
“Using the Alternate CMU Transmitter PLL” on page
clock
mux
clock
mux
shows the functional blocks that you can dynamically reconfigure using
CMU Channel
CMU0 PLL
CMU1 PLL
Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Logical
TX PLL
select
clock
mux
Dynamic Reconfiguration Modes Implementation
Full Duplex Transceiver Channel
DIVIDER
LOCAL
TX CHANNEL
RX CHANNEL
RX CDR
February 2011 Altera Corporation
5–27.
TX PMA + TX PCS
5–60.
RX PMA + RX PCS