EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 452

• Manufacturer Part Number: EP4SE530H35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 744
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

1–8
Table 1–4. Stratix IV GT Device Offerings and Transceiver Channels Available in Each Device
Stratix IV Device Handbook Volume 2: Transceivers
Total
Transceiver
Channels
10G Transceiver
Channels
8G Transceiver
Channels
CMU Channels
(PMA-only)
Notes to
(1) 10G transceiver channels support data rates between 600 Mbps and 11.3 Gbps.
(2) 8G transceiver channels support data rates between 600 Mbps and 8.5 Gbps. All 10G transceiver channels can also be configured as 8G transceiver
(3) CMU channels that support data rates between 600 Mbps and 6.5 Gbps are PMA-only channels that do not have PCS circuitry. For more
(4) F40 devices use 1517-pin flip chip packages. H40 devices use 1517-pin hybrid flip chip packages. F45 devices use 1932-pin flip chip packages.
Transceiver
Channels
channels. For example, the EP4S40G2F40 device has twenty-four 8G transceiver channels and the EP4S100G5F45 device has thirty-two 8G
transceiver channels.
information, refer to
Table
Stratix IV GT Device Offerings
(1)
(2)
(3)
1–4:
EP4S40G2F40
“CMU Channel Architecture” on page
Table 1–4
channels available in each device.
Table 1–5
transceiver channels up to 11.3 Gbps.
Table 1–5. Transceiver Blocks in Stratix IV GT Devices Supporting Transceiver Channels up to
11.3 Gbps (Part 1 of 2)
EP4S40G2F40
EP4S40G5H40
36
12
12
12
(4)
Device Member
lists the Stratix IV GT device offerings along with the number of transceiver
lists the transceiver blocks in each Stratix IV GT device that support
EP4S40G5H40
36
12
12
12
Total number of Transceiver
1–100.
EP4S100G2F40
Channels
36
24
12
(4)
0
36
36
EP4S100G5H40
Chapter 1: Transceiver Architecture in Stratix IV Devices
36
24
12
0
12 regular transceiver channels (six 10G
and six 8G), located in three transceiver
blocks:
Left Side—4 in GXBL2, 2 in GXBL1
Right Side—4 in GXBR2, 2 in GXBR1
Refer to
12 regular transceiver channels (six 10G
and six 8G), located in three transceiver
blocks:
Left Side—4 in GXBL2, 4 in GXBL1, 4 in
GXBL0
Right Side—4 in GXBR2, 4 in GXBR1, 4 in
GXBR0
Refer to
Transceiver Channel Location
Figure 1–5 on page
Figure 1–6 on page
EP4S100G3F45,
EP4S100G4F45
February 2011 Altera Corporation
Transceiver Channel Locations
48
24
16
8
1–10.
1–11.
EP4S100G5F45
48
32
16
0