EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 461

• Manufacturer Part Number: EP4SE530H35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 744
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Figure 1–12. Stratix IV GX and GT Transceiver Datapath
February 2011 Altera Corporation
FPGA
Fabric
Transceiver Channel Architecture
1
The Stratix IV GT transceiver architecture has the following components:
■
■
■
Four transceiver channels and two CMU channels are located in each transceiver
block on the left and right sides of the device. Each Stratix IV GT device also has two
10G ATX PLLs that support data rates between 9.9 Gbps and 11.3 Gbps. Additionally,
each Stratix IV GT device has two 6G ATX PLLs that support data rates between
600 Mbps and 6.5 Gbps, except the EP4S100G5F45 device that has four 6G ATX PLLs.
The 6G ATX PLL does not support all data rates between 600 Mbps and 6.5 Gbps.
Figure 1–12
Each transceiver channel consists of the:
■
■
Each transceiver channel interfaces to either the PCIe hard IP block (PCIe hard
IP-transceiver interface) or directly to the FPGA fabric (FPGA fabric-transceiver
interface). The transceiver channel interfaces to the PCIe hard IP block if the hard IP
block is used to implement the PCIe PHY MAC, data link layer, and transaction layer.
Otherwise, the transceiver channel interfaces directly to the FPGA fabric.
Regular transceiver channels with PMA and PCS support
CMU channels with PMA-only support
ATX PLL blocks
Transmitter channel, further divided into:
■
■
Receiver channel, further divided into:
■
■
Transmitter channel PCS
Transmitter channel PMA
Receiver channel PCS
Receiver channel PMA
Compensation
wrclk
shows the Stratix IV GX and GT transceiver channel datapath.
TX Phase
FIFO
rdclk
Byte Serializer
wrclk
Receiver Channel PCS
Transmitter Channel PCS
rdclk
Transmitter Channel Datapath
Receiver Channel Datapath
8B/10B Encoder
Stratix IV Device Handbook Volume 2: Transceivers
Transmitter Channel
Receiver Channel
PMA
PMA
1–17