EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 119

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EP4SE530H35C2N

Manufacturer Part Number
EP4SE530H35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
STRATIX® IV Er

Specifications of EP4SE530H35C2N

Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
744
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

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Chapter 5: Clock Networks and PLLs in Stratix IV Devices
Clock Networks in Stratix IV Devices
Figure 5–1. GCLK Networks
February 2011 Altera Corporation
Global Clock Networks
Stratix IV devices provide up to 16 GCLKs that can drive throughout the device,
serving as low-skew clock sources for functional blocks such as adaptive logic
modules (ALMs), digital signal processing (DSP) blocks, TriMatrix memory blocks,
and PLLs. Stratix IV device I/O elements (IOEs) and internal logic can also drive
GCLKs to create internally generated global clocks and other high fan-out control
signals; for example, synchronous or asynchronous clears and clock enables.
Figure 5–1
Stratix IV devices.
CLK[0..3]
shows the CLK pins and PLLs that can drive the GCLK networks in
L1
L2
L3
L4
GCLK[0..3]
GCLK[12..15]
GCLK[4..7]
CLK[12..15]
CLK[4..7]
T1 T2
B1 B2
GCLK[8..11]
R1
R2
R3
R4
CLK[8..11]
Stratix IV Device Handbook Volume 1
5–3

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