EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 825

• Manufacturer Part Number: EP4SE530H35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 744
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 4: Reset Control and Power Down in Stratix IV Devices
Transceiver Reset Sequences
February 2011 Altera Corporation
As shown in
reset steps:
1. After power up, assert pll_powerdown for a minimum period of t
2. Keep the tx_digitalreset, rx_analogreset, and rx_digitalreset signals
3. After the transmitter PLL locks, as indicated by the pll_locked signal going high
4. Wait for the rx_freqlocked signal to go high (marker 7).
5. After the rx_freqlocked signal goes high, wait for at least t
time between markers 1 and 2).
asserted during this time period. After you de-assert the pll_powerdown signal, the
transmitter PLL starts locking to the transmitter input reference clock.
(marker 3), de-assert tx_digitalreset. For receiver operation, wait for the busy
signal to be de-asserted, after which rx_analogreset is de-asserted. After you
de-assert rx_analogreset, the receiver CDR starts locking to the receiver input
reference clock.
the rx_digitalreset signal (marker 8). Note that rx_digitalreset must not be
released if there is no data present at the receiver pins to avoid
overflow/underflow of the phase compensation FIFOs. At this point, the
transmitter and receiver are ready for data traffic.
Figure
4–10, for the receiver in CDR automatic lock mode, follow these
Stratix IV Device Handbook Volume 2: Transceivers
LTD_Auto
pll_powerdown
, then de-assert
(the
4–19