EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 300

• Manufacturer Part Number: EP4SE530H35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 744
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

8–22
Figure 8–17. Deserializer Bypass in Stratix IV Devices
Notes to
(1) All disabled blocks and signals are grayed out.
(2) In DDR mode, rx_inclock clocks the IOE register. In SDR mode, data is directly passed through the IOE.
(3) In SDR and DDR modes, the data width from the IOE is 1 and 2 bits, respectively.
Stratix IV Device Handbook Volume 1
rx_divfwdclk
rx_outclock
Fabric
FPGA
rx_out
Figure
Receiver Data Path Modes
8–17:
2
Deserializer
You can statically set the deserialization factor to 3, 4, 6, 7, 8, or 10 by using the
Quartus II software. You can bypass the Stratix IV deserializer in the Quartus II
MegaWizard Plug-In Manager software to support DDR (×2) or SDR (×1) operations,
as shown
deserializer is bypassed. The IOE contains two data input registers that can operate in
DDR or SDR mode.
The Stratix IV device family supports three receiver datapath modes—non-DPA
mode, DPA mode, and soft-CDR mode.
Non-DPA Mode
Figure 8–18
and synchronizer blocks are disabled. Input serial data is registered at the rising or
falling edge of the serial LVDS_diffioclk clock produced by the left and right PLL.
You can select the rising/falling edge option using the ALTLDVS MegaWizard
Plug-In Manager software. Both data realignment and deserializer blocks are clocked
by the LVDS_diffioclk clock, which is generated by the left and right PLL.
IOE Supports SDR, DDR, or Non-Registered Datapath
(LOAD_EN, diffioclk)
2
Deserializer
Deserializer
Figure
DOUT DIN
shows the non-DPA datapath block diagram. In non-DPA mode, the DPA
8–17. The DPA and data realignment circuit cannot be used when the
IOE
2
Left/Right PLL
Left/Right PLL
3
DOUT DIN
Clock Mux
Bit Slip
(LVDS_LOAD_EN,
LVDS_diffioclk,
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
rx_outclk)
(Note
diffioclk
1), (2),
(3)
8 Serial LVDS
Clock Phases
Synchronizer
DOUT DIN
LVDS Receiver
3
(DPA_LOAD_EN,
DPA_diffioclk,
rx_divfwdclk)
February 2011 Altera Corporation
Retimed
DPA Circuitry
DPA Clock
Data
DIN
Differential Receiver
+
rx_in