EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 503

• Manufacturer Part Number: EP4SE530H35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 744
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Figure 1–48. Deserializer Bit Order in Single-Width Mode
February 2011 Altera Corporation
Low-Speed Parallel Clock
High-Speed Serial Clock
dataout
Figure 1–48
data output of the deserializer block in single-width mode with a 10-bit
deserialization factor. The serial stream (0101111100) is deserialized to a value 10'h17C.
The serial data is assumed to be received LSB to MSB.
Word Aligner
Because the data is serialized before transmission and then deserialized at the
receiver, it loses the word boundary of the upstream transmitter upon deserialization.
The word aligner receives parallel data from the deserializer and restores the word
boundary based on a pre-defined alignment pattern that must be received during link
synchronization.
Serial protocols such as PCIe, XAUI, Gigabit Ethernet, Serial RapidIO, and
SONET/SDH, specify a standard word alignment pattern. For proprietary protocols,
the Stratix IV GX and GT transceiver architecture allows you to select a custom word
alignment pattern specific to your implementation.
In addition to restoring the word boundary, the word aligner also implements the
following features:
■
■
■
■
■
Depending on the configured functional mode, the word aligner operates in one of
the following three modes:
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■
■
datain
Synchronization state machine in functional modes such as PCIe, XAUI, GIGE,
Serial RapidIO, and Basic single-width
Programmable run length violation detection in all functional modes
Receiver polarity inversion in all functional modes except PCIe
Receiver bit reversal in Basic single-width and Basic double-width modes
Receiver byte reversal in Basic double-width modes
Manual alignment mode
Automatic synchronization state machine mode
Bit-slip mode
0
shows the serial bit order of the deserializer block input and the parallel
0 1 1 1 1
1 0 1 0 1 1 0 0 0 0 0 1 0 1
0101111100
Stratix IV Device Handbook Volume 2: Transceivers
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1–59