EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 1033

• Manufacturer Part Number: EP4SE530H35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 744
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 2: Transceiver Design Flow Guide for Stratix IV Devices
Guidelines to Debug Transceiver-Based Designs
February 2011 Altera Corporation
Guidelines to Debug the FPGA Logic and the Transceiver Interface
Before checking the functionality in silicon, perform functional simulation to ensure
the basic functionality of the RTL and the transceiver-FPGA fabric interface.
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Understand the limitations of functional simulation. If you intend to simulate
timing parameters, consider post-fit simulation. The functional simulation model
for transceivers does not model timing-related parameters or uncertainties in the
transceiver data path. For example, the PPM difference in the rate matcher clocks
(clock rate compensation) or the phase differences between the read and write side
of the phase compensation FIFO are not modeled.
f
Check whether the compiled design has timing violations in the TimeQuest
Timing Analyzer report. Set the appropriate timing constraints on the failing
paths.
f
Verify the functionality of the transmitter and receiver data path with serial
loopback. Dynamically control the serial loopback through the rx_seriallpbken
port. When this signal is asserted, data from the transmitter serializer is looped
back to the receiver CDR of the channel.
Use SignalTap to verify the behavior of the user logic and the transceiver interface
signals. If you have FPGA I/O pins available for debug, you can also use the
external logic analyzer to debug the functionality of the device.
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Verify the interconnect on the receive side by configuring the transceiver in reverse
serial loopback mode. In this case, the recovered data from the receiver channel is
sent to the transmitter buffer. To configure a transceiver channel operating in a
different configuration to reverse serial loopback mode, use the dynamic
reconfiguration controller.
Check whether the transceiver FPGA fabric interface clocking schemes follow the
recommendations provided in the “FPGA Fabric-Transceiver Interface Clocking”
section in the
Ensure that you have used the recommended transceiver reset sequence.
For information about functional RTL simulation or post-fit simulation,
refer to the
For information about using the TimeQuest Timing Analyzer, refer to the
The Quartus II TimeQuest Timing Analyzer
Quartus II Handbook.
For more information, refer to the
Analyzers
To use these features, you must connect the JTAG configuration pins in the
FPGA.
Transceiver Clocking in Stratix IV Devices
chapter in volume 3 of the Quartus II Handbook.
Simulation
chapter in volume 3 of the Quartus II Handbook.
In-System Debugging Using External Logic
chapter in volume 3 of the
chapter.
Stratix IV Device Handbook Volume 3
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