EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 765

• Manufacturer Part Number: EP4SE530H35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 744
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices
Combining Transmitter Channel and Receiver Channel Instances
Combining Transmitter Channel and Receiver Channel Instances
February 2011 Altera Corporation
Multiple Transmitter Channel and Receiver Channel Instances
You can create separate transmitter and receiver channel instances and assign the
tx_dataout and rx_datain pins of the transmitter and receiver instances, respectively,
to the same physical transceiver channel. This configuration is useful when you
intend to run the transmitter and receiver channel at different serial data rates. To
create separate transmitter and receiver channel instances, select the Transmitter only
and Receiver only options in the operating mode (General screen) of the ALTGX
MegaWizard Plug-In Manager.
The Quartus II software allows you to combine multiple Transmitter only and
Receiver only channel instances within the same transceiver block. Based on the pin
assignments, the Quartus II software combines the corresponding Transmitter only
and Receiver only channels in the same physical channel. To enable the Quartus II
software to combine the transmitter channel and receiver channel instances in the
same transceiver block, follow the rules and requirements outlined in:
■
■
■
Example 3
Consider the example design listed in
Table 3–5. Four ALTGX Instances for Example 3
After you create the above instances, if you force the placement of the instances, as
listed in
channel 0, and inst2 and inst3 to physical channel 1.
Table 3–6. Forced Placement of the Instances for Example 3
Instance Name
“General Requirements to Combine Channels” on page 3–3
“Multiple Channels Sharing a CMU PLL” on page 3–5
“Combining Receiver Only Channels” on page 3–10
inst0
inst1
inst2
inst3
Table
Instance Name
inst0
inst1
inst2
inst3
3–6, the Quartus II software combines inst0 and inst1 to physical
Transmitter only
Transmitter only
Configuration
Receiver only
Receiver only
Serial Data Rate
Table 3–5
Physical Channel Pin Assignments in the Same
(Gbps)
3.125
1.25
2.5
2
with four ALTGX instances.
Stratix IV Device Handbook Volume 2: Transceivers
RX pin of channel 0
RX pin of channel 1
TX pin of channel 0
TX pin of channel 1
Transceiver Block
Input Reference Clock Frequency
156.25
156.25
(MHz)
125
125
3–11