EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 493

• Manufacturer Part Number: EP4SE530H35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 744
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Table 1–23. Allowed DC-Coupling Scenarios for Stratix IV GT Devices (Part 2 of 2)
February 2011 Altera Corporation
Stratix II GX Transmitter
(1.5-V PCML)
Third-Party LVDS Transmitter
(Transmitter I/O Standard)
From
1
The transfer function of the physical medium can be represented as a low-pass filter in
the frequency domain. Frequency components below –3 dB frequency pass through
with minimal loss. Frequency components greater than –3 dB frequency are
attenuated as a function of frequency due to skin-effect and dielectric losses. This
variation in frequency response yields data-dependent jitter and other ISI effects,
which can cause incorrect sampling of the input data.
Each Stratix IV GX and GT receiver buffer has independently programmable
equalization circuitry that boosts the high-frequency gain of the incoming signal,
thereby compensating for the low-pass filter effects of the physical medium. The
amount of high-frequency gain required depends on the loss characteristics of the
physical medium. Stratix IV GX and GT equalization circuitry supports 16
equalization settings that provide up to 16 dB of high-frequency boost. You can select
the appropriate equalization setting in the ALTGX MegaWizard Plug-In Manager.
Stratix IV GX and GT receiver buffers also support programmable DC gain circuitry.
Unlike equalization circuitry, DC gain circuitry provides equal boost to the incoming
signal across the frequency spectrum. The receiver buffer supports DC gain settings of
0, 3, 6, 9, and 12 dB. You can select the appropriate DC gain setting in the ALTGX
MegaWizard Plug-In Manager.
In PCIe mode, you can enable the optional signal threshold detection circuitry by not
selecting the Force signal detection option in the ALTGX MegaWizard Plug-In
Manager. If enabled, this option senses whether the signal level present at the receiver
input buffer is above the signal detect threshold voltage that you specified in the
What is the signal detect and signal loss threshold? option in the ALTGX
MegaWizard Plug-In Manager.
The appropriate signal detect threshold level that complies with the PCIe compliance
parameter VRX-IDLE-DETDIFFp-p is available in the
chapter.
Signal threshold detection circuitry has a hysteresis response that filters out any
high-frequency ringing caused by inter-symbol interference or high-frequency losses
in the transmission medium. If the signal threshold detection circuitry senses the
signal level present at the receiver input buffer to be higher than the signal detect
threshold, it asserts the rx_signaldetect signal high. Otherwise, the signal threshold
detection circuitry de-asserts the rx_signaldetect signal low.
Programmable Equalization and DC Gain
Signal Threshold Detection Circuitry
Stratix IV GT Receiver
(1.4-V PCML)
Stratix IV GT Receiver
(LVDS)
(Receiver I/O Standard)
To
600 Mbps to 6.375 Gbps
600 Mbps to 6.5 Gbps
Data Rate Range
Stratix IV Device Handbook Volume 2: Transceivers
DC and Switching Characteristics
■
■
■
■
TX V
(600 Mbps to 3.125 Gbps)
TX V
(3.125 Gbps to 6.375 Gbps)
RX V
RX V
CM
CM
CM
CM
Conditions
= 0.7 V
= 0.6 V
= 0.82 V
= 1.1 V
1–49