EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 291
EP4SE530H35C2N
Manufacturer Part Number
EP4SE530H35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
744
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4SE530H35C2N
Manufacturer:
ALTERA
Quantity:
147
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- EP4SE230F29C3N PDF datasheet #6
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Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Differential Transmitter
Figure 8–7. Serializer Bypass in Stratix IV Devices
Notes to
(1) All disabled blocks and signals are grayed out.
(2) In DDR mode, tx_inclock clocks the IOE register. In SDR mode, data is directly passed through the IOE.
(3) In SDR and DDR modes, the data width to the IOE is 1 and 2 bits, respectively.
February 2011 Altera Corporation
Figure
(LVDS_LOAD_EN, diffioclk, tx_coreclock)
(LVDS_LOAD_EN, diffioclk, tx_coreclock)
8–7:
tx_coreclock
tx_coreclock
Figure 8–6
mode, you can use an LVDS channel as a clock output channel.
Figure 8–6. Stratix IV Transmitter in Clock Output Mode
You can bypass the Stratix IV serializer to support DDR (×2) and SDR (×1) operations
to achieve a serialization factor of 2 and 1, respectively. The I/O element (IOE)
contains two data output registers that can each operate in either DDR or SDR mode.
Figure 8–7
FPGA
Fabric
tx_in 2
shows the Stratix IV transmitter in clock output mode. In clock output
shows the serializer bypass path.
FPGA
Fabric
Left/Right PLL
Left/Right PLL
DIN
DIN
Serializer
Serializer
3
DOUT
DOUT
(Note
2
Left/Right
PLL
IOE
1), (2),
Parallel
Transmitter Circuit
LVDS_LOAD_EN
diffioclk
(3)
LVDS Transmitter
Series
IOE supports SDR, DDR, or
Non-Registered Datapath
Stratix IV Device Handbook Volume 1
+
-
Txclkout+
Txclkout–
tx_out
8–13
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