EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 515

• Manufacturer Part Number: EP4SE530H35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 744
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
February 2011 Altera Corporation
The programmable run length violation circuit resides in the word aligner block and
detects consecutive 1s or 0s in the data. If the data stream exceeds the preset
maximum number of consecutive 1s or 0s, the violation is signified by the assertion of
the rx_rlv signal.
The run length violation status signal on the rx_rlv port has lower latency when
compared with the parallel data on the rx_dataout port. The rx_rlv signal in each
channel is clocked by its parallel recovered clock. The FPGA fabric clock might have
phase difference and/or PPM difference (in asynchronous systems) with respect to
the recovered clock. To ensure that the FPGA fabric clock can latch the rx_rlv signal
reliably, the run length violation circuitry asserts the rx_rlv signal for a minimum of
two recovered clock cycles in single-width modes and a minimum of three recovered
clock cycles in double-width modes. The rx_rlv signal can be asserted longer,
depending on the run length of the received data.
In single-width mode, the run length violation circuit detects up to a run length of 128
(for an 8-bit deserialization factor) or 160 (for a 10-bit deserialization factor). The
settings are in increments of four or five for the 8-bit or 10-bit deserialization factors,
respectively.
In double-width mode, the run length violation circuit maximum run length detection
is 512 (with a run length increment of eight) and 640 (with a run length increment of
10) for the 16-bit and 20-bit deserialization factors, respectively.
Table 1–32
Table 1–32. Detection Capabilities of the Run Length Violation Circuit
The positive and negative signals of a serial differential link are often erroneously
swapped during board layout. Solutions like board re-spin or major updates to the
PLD logic can be expensive. The receiver polarity inversion feature is provided to
correct this situation.
An optional rx_invpolarity port is available in all single-width and double-width
modes except (OIF) CEI PHY and PCIe modes to dynamically enable the receiver
polarity inversion feature. In single-width modes, a high value on the rx_invpolarity
port inverts the polarity of every bit of the 8-bit or 10-bit input data word to the word
aligner in the receiver datapath. In double-width modes, a high value on the
rx_invpolarity port inverts the polarity of every bit of the 16-bit or 20-bit input data
word to the word aligner in the receiver datapath. Because inverting the polarity of
each bit has the same effect as swapping the positive and negative signals of the
differential link, correct data is seen by the receiver. rx_invpolarity is a dynamic
signal and can cause initial disparity errors in an 8B/10B encoded link. The
downstream system must be able to tolerate these disparity errors.
Single-width mode
Double-width mode
Programmable Run Length Violation Detection
Receiver Polarity Inversion
Mode
lists the detection capabilities of the run length violation circuit.
PMA-PCS Interface
Width
10-bit
16-bit
20-bit
8-bit
Run Length Violation Detector Range
Stratix IV Device Handbook Volume 2: Transceivers
Minimum
10
4
5
8
Maximum
128
160
512
640
1–71