EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 525

• Manufacturer Part Number: EP4SE530H35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 744
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Figure 1–64. Rate Match Deletion in XAUI Mode
February 2011 Altera Corporation
rx_rmfifodatadeleted
Before Rate Match:
After Rate Match:
dataout[3]
dataout[2]
dataout[1]
dataout[0]
datain[3]
datain[2]
datain[1]
datain[0]
Two flags, rx_rmfifodatadeleted and rx_rmfifodatainserted, that indicate rate
match FIFO deletion and insertion events, respectively, are forwarded to the FPGA
fabric. If an ||R|| column is deleted, the rx_rmfifodeleted flag from each of the
four channels goes high for one clock cycle per deleted ||R|| column. If an ||R||
column is inserted, the rx_rmfifoinserted flag from each of the four channels goes
high for one clock cycle per inserted ||R|| column.
Figure 1–64
columns must be deleted.
K28.5
K28.5
K28.5
K28.5
K28.5
K28.5
K28.5
K28.5
K28.3
K28.3
K28.3
K28.3
K28.3
K28.3
K28.3
K28.3
shows an example of rate match deletion in the case where three ||R||
K28.5
K28.5
K28.5
K28.5
K28.5
K28.5
K28.5
K28.5
First ||R||
Column
K28.5
K28.5
K28.5
K28.5
K28.0
K28.0
K28.0
K28.0
K28.0
K28.0
K28.0
K28.0
K28.5
K28.5
K28.5
K28.5
Second ||R||
Column
K28.5
K28.5
K28.5
K28.5
K28.0
K28.0
K28.0
K28.0
Stratix IV Device Handbook Volume 2: Transceivers
Third ||R||
Column
K28.0
K28.0
K28.0
K28.0
Fourth ||R||
Column
K28.0
K28.0
K28.0
K28.0
K28.5
K28.5
K28.5
K28.5
1–81