EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 824

• Manufacturer Part Number: EP4SE530H35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 744
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

4–18
Figure 4–10. Sample Reset Sequence of Receiver and Transmitter Channel—Receiver CDR in Automatic Lock Mode
Notes to
(1) For t
(2) For t
Stratix IV Device Handbook Volume 2: Transceivers
Output Status Signals
Figure
pll_powerdown
LTD_Auto
Reset Signals
pll _ powerdown
rx _ analogreset
4–10:
tx _ digitalreset
rx _ digitalreset
duration, refer to the
rx _ freqlocked
pll _locked
duration, refer to the
busy
As shown in
steps:
1. After power up, wait for the busy signal to be asserted.
2. Keep the rx_digitalreset and rx_locktorefclk signals asserted and the
3. After de-assertion of the busy signal, de-assert the rx_analogreset signal. The
4. Wait for at least t
5. De-assert rx_digitalreset at least t
Receiver and Transmitter Channel—Receiver CDR in Automatic Lock Mode
This configuration contains both a transmitter and a receiver channel. If you create a
Receiver and Transmitter instance in the ALTGX MegaWizard Plug-In Manager with
the receiver CDR in automatic lock mode, use the reset sequence shown in
Figure
rx_locktodata signal de-asserted during this time period.
receiver CDR then starts locking to the receiver input reference clock because the
rx_locktorefclk signal is asserted.
rx_pll_locked signal goes high and then de-assert the rx_locktorefclk signal. At
the same time, assert the rx_locktodata signal (marker 4). At this point, the
receiver CDR enters lock-to-data mode and the receiver PLL starts locking to the
received data.
5) after asserting the rx_locktodata signal.
1
t
pll_powerdown (1)
4–10.
DC and Switching Characteristics for Stratix IV Devices
DC and Switching Characteristics for Stratix IV Devices
Figure
2
4–9, for the receiver CDR in manual lock mode, follow these reset
LTR_LTD_Manual
3
4
Two parallel clock cycles
5
6
time (the time between markers 3 and 4) after the
Chapter 4: Reset Control and Power Down in Stratix IV Devices
LTD_Manual
7
t
LTD_Auto (2)
chapter.
chapter.
(the time between markers 4 and
8
February 2011 Altera Corporation
Transceiver Reset Sequences