EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 165

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EP4SE530H35C2N

Manufacturer Part Number
EP4SE530H35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
STRATIX® IV Er

Specifications of EP4SE530H35C2N

Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
744
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

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Chapter 5: Clock Networks and PLLs in Stratix IV Devices
PLLs in Stratix IV Devices
February 2011 Altera Corporation
Charge Pump and Loop Filter
You can reconfigure the charge-pump and loop-filter settings to update the PLL
bandwidth in real time.
Table 5–12
Stratix IV PLLs.
Table 5–12. Charge Pump Current Bit Settings
Table 5–13
PLLs.
Table 5–13. Loop-Filter Resistor Bit Settings
Table 5–14
PLLs.
Table 5–14. Loop-Filter Capacitor Bit Settings
LFR[4]
0
0
0
0
1
1
1
1
1
1
1
CP[2]
0
0
0
1
LFC[1]
lists the possible settings for charge pump current (Icp) values for
lists the possible settings for loop-filter resistor (R) values for Stratix IV
lists the possible settings for loop-filter capacitor (C) values for Stratix IV
0
0
1
LFR[3]
0
0
0
1
0
0
0
1
1
1
1
CP[1]
0
0
1
1
LFR[2]
0
0
1
0
0
0
1
0
0
1
1
LFC[0]
0
1
1
LFR[1]
0
1
0
0
0
1
0
0
1
0
1
CP[0]
0
1
1
1
LFR[0]
0
1
0
0
0
1
0
0
1
0
0
Decimal Value for Setting
Decimal Value for Setting
Stratix IV Device Handbook Volume 1
Decimal Value for Setting
0
1
3
0
3
7
1
16
19
20
24
27
28
30
0
3
4
8
5–49

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