EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 815

• Manufacturer Part Number: EP4SE530H35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 744
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 4: Reset Control and Power Down in Stratix IV Devices
Transceiver Reset Sequences
February 2011 Altera Corporation
As shown in
follow these reset steps:
1. After power up, assert pll_powerdown for a minimum period of t
2. Keep the tx_digitalreset, rx_analogreset, and rx_digitalreset signals
3. After the transmitter PLL locks, as indicated by the pll_locked signal going high,
4. For the receiver operation, after de-assertion of busy signal, wait for a minimum of
5. Wait for the rx_freqlocked signal from each channel to go high. The
6. In a bonded channel group, when the rx_freqlocked signals of all the channels
time between markers 1 and 2).
asserted during this time period. After you de-assert the pll_powerdown signal, the
transmitter PLL starts locking to the transmitter input reference clock.
de-assert the tx_digitalreset signal. At this point, the transmitter is ready for
data traffic.
two parallel clock cycles to de-assert the rx_analogreset signal. After
rx_analogreset is de-asserted, the receiver CDR of each channel starts locking to
the receiver input reference clock.
rx_freqlocked signal of each channel may go high at different times (indicated by
the slashed pattern at marker 7).
has gone high, from that point onwards, wait for at least t
parallel clock to be stable, then de-assert the rx_digitalreset signal (marker 8).
At this point, all the receivers are ready for data traffic. Note that rx_digitalreset
must not be released if there is no data present at the receiver pins to avoid
overflow/underflow of the phase compensation FIFOs.
Figure
4–4, for the receiver CDR in automatic lock mode configuration,
Stratix IV Device Handbook Volume 2: Transceivers
LTD_Auto
pll_powerdown
for the receiver
(the
4–9