EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 65

• Manufacturer Part Number: EP4SE530H35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 744
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices
Memory Modes
February 2011 Altera Corporation
Single-Port RAM Mode
All TriMatrix memory blocks support single-port mode. Single-port mode allows you
to do either one-read or one-write operation at a time. Simultaneous reads and writes
are not supported in single-port mode.
configuration.
Figure 3–7. Single-Port RAM
Note to
(1) You can implement two single-port memory blocks in a single M9K or M144K block. For more information, refer to
During a write operation, RAM output behavior is configurable. If you use the
read-enable signal and perform a write operation with read enable de-activated, the
RAM outputs retain the values they held during the most recent active read enable. If
you activate read enable during a write operation, or if you are not using the
read-enable signal at all, the RAM outputs either show the “new data” being written,
the “old data” at that address, or a “don’t care” value. To choose the desired behavior,
set the read-during-write behavior to either new data, old data, or don’t care in the
RAM MegaWizard Plug-In Manager in the Quartus II software. For more information,
refer to
Table 3–4
single-port mode.
Table 3–4. Port Width Configurations for MLABs, M9K, and M144K Blocks (Single-Port Mode)
Port Width
Configurations
“Packed Mode Support” on page
Figure
“Read-During-Write Behavior” on page
lists the possible port width configurations for TriMatrix memory blocks in
3–7:
64 × 10
32 × 16
32 × 18
32 × 20
(Note 1)
3–4.
MLABs
data[ ]
address[ ]
wren
byteena[]
addressstall
clockena
rden
aclr
64 × 8
64 × 9
inclock
Figure 3–7
M9K Blocks
3–18.
512 × 16
512 × 18
256 × 32
256 × 36
8K × 1
4K × 2
2K × 4
1K × 8
1K × 9
shows the single-port RAM
outclock
q[]
Stratix IV Device Handbook Volume 1
M144K Blocks
16K × 8
16K × 9
8K × 16
8K × 18
4K × 32
4K × 36
2K × 64
2K × 72
3–9