EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 496

• Manufacturer Part Number: EP4SE530H35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 744
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

1–52
Figure 1–44. Receiver Channel Data Path showing the EyeQ Feature
Stratix IV Device Handbook Volume 2: Transceivers
reconfig_mode_sel[3:0]
ctrl_writedata[15:0]
f
1
1
ALTGX_RECONFIG Instance
ctrl_address[15:0]
EyeQ Control
Normally, the receiver CDR samples the incoming signal at the center of the eye.
When you enable the EyeQ hardware, it allows the CDR to sample across 32 different
positions within one unit interval (UI) of a data eye. You can manually control the
sampling points and check the bit-error rate (BER) at each of these 32 sampling points.
At the center of the eye, the BER is 0. As the sampling point is moved away from the
center of the eye towards an edge, the BER increases. By observing sampling points
with 0 BER and sampling points with higher BER, you can determine the eye width.
The EyeQ hardware is available for both regular transceiver channels and CMU
channels.
The EyeQ block resides within the PMA of the receiver channel and is available for
both the transceiver channels and CMU channels of a transceiver block.
shows the EyeQ feature within a receiver channel datapath.
You must implement logic to check the bit error rate (BER). This includes a pattern
generator and checker.
Figure 1–44
For more information about using the EyeQ feature, refer to the
Reconfiguration in Stratix IV Devices
Block
ctrl_readdata[15:0]
ctrl_write
ctrl_waitrequest
ctrl_read
error
shows the receiver channel data path using the EyeQ feature.
busy
reconfig_fromgxb[17:0]
reconfig_togxb[3:0]
chapter.
Chapter 1: Transceiver Architecture in Stratix IV Devices
Receiver Channel 0
EyeQ Hardware
ALTGX Instance
February 2011 Altera Corporation
Transceiver Block Architecture
Dynamic
Figure 1–44
rx_datain[0]