EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 668

• Manufacturer Part Number: EP4SE530H35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 744
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

1–224
Table 1–78. Stratix IV GX and GT ALTGX Megafunction Ports: Reset and Power Down (Part 2 of 2)
Table 1–79. Stratix IV GX and GT ALTGX Megafunction Ports: Calibration Block
Reference Information
Stratix IV Device Handbook Volume 2: Transceivers
rx_analogreset
tx_digitalreset
cal_blk_clk
cal_blk_powerdown
Port Name
Port Name
Table 1–79
Use the links listed in
terms used in this chapter.
Table 1–80. Reference Information (Part 1 of 3)
Basic (PMA Direct) Functional Mode
Clock and Data Recovery Unit (CDR)
Auxiliary Transmit (ATX) PLL Block
Output
Output
(OIF) CEI PHY Interface Mode
Input/
Input/
Input
Input
Input
Input
Terms Used in this Chapter
CMU Channel Architecture
lists the ALTGX megafunction calibration block ports.
Built-In Self Test Modes
Basic Functional Mode
Byte Ordering Block
Calibration Blocks
8B/10B Decoder
8B/10B Encoder
Byte Serializer
CMU0 PLL
CMU1 PLL
Clock Domain
Asynchronous
Asynchronous
pulse width is
pulse width is
Clock Domain
clock cycles.
clock cycles.
two parallel
two parallel
AEQ
Clock signal
Clock signal
Minimum
Minimum
signal.
signal.
Table 1–80
Receiver PMA reset.
■
Transmitter PCS reset.
■
for more information about some useful reference
Clock for transceiver calibration blocks.
Calibration block power down control.
When asserted high—analog circuitry within the
receiver PMA gets reset. Refer to
Power Down.
When asserted high, the transmitter PCS blocks
are reset. Refer to
Chapter 1: Transceiver Architecture in Stratix IV Devices
Description
Reset Control and Power Down.
Description
Useful Reference Points
page 1–181
page 1–195
page 1–187
page 1–111
page 1–206
page 1–201
page 1–100
page 1–102
page 1–102
page 1–89
page 1–23
page 1–50
page 1–95
page 1–93
page 1–53
February 2011 Altera Corporation
Reset Control and
Reference Information
Channel
Channel
Scope
Scope
Device
Device