EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 710

• Manufacturer Part Number: EP4SE530H35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 744
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

2–38
Stratix IV Device Handbook Volume 2: Transceivers
f
f
1
1
For more examples regarding this clocking scheme, refer to:
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In Basic (PMA-Direct) ×N mode, the CMU0 channel distributes the transceiver clocks to
the channels placed in the same transceiver block using the ×4 clock lines. The ×4
clock lines drive the ×N_Top and ×N_Bottom clock lines to distribute the transceiver
clocks to the transmitter channels located in transceiver blocks on the bottom and top.
The difference in clock routing delays between the ×4 clock lines and the ×N clock
lines can result in higher transmitter channel-to-channel skew. To compensate for this
difference in clock routing delays between the ×4 and the ×N clock lines, the Stratix IV
transceivers introduce a fixed amount of delay in the ×4 clock lines of the transceiver
block whose CMU0 channel generates the transceiver clocks.
The delay compensation mechanism engaged in Basic (PMA Direct) mode only
compensates for the clock routing delays between the transceiver block whose CMU0
channel generates the transceiver clocks and its adjacent transceiver block located
above and below.
To minimize transmitter channel-to-channel skew in ×N bonded channels, use the
recommended placement shown in
Table 2–8. Recommended Placement of Channels and CMU in Bonded Modes
If you use the ATX PLL to generate the transceiver clocks, Altera recommends placing
the channels in the transceiver blocks adjacent to the ATX PLL on both sides of the
ATX PLL.
For manual placement of the CMU and ATX PLLs, if the Quartus II software does not
automatically pick the most optimal location for skew, refer to
Placement of CMU PLLs and ATX PLLs in Stratix IV GX and GT
“Example 1: Channel Configuration with a 4 Gbps Data Rate” on page 2–9
AN 571: Implementing the SERDES Framer Interface Level 5 (SFI-5.1) Protocol in
Stratix IV Devices
AN 572: Implementing the Scalable SERDES Framer Interface (SFI-S) Protocol in
Stratix IV GT Devices
Transmitter Channel-to-Channel Skew Optimization in Basic (PMA Direct) ×N Mode
2 adjacent transceiver blocks
3 adjacent transceiver blocks
4 adjacent transceiver blocks
Channel Placement
Table
2–8.
Chapter 2: Transceiver Clocking in Stratix IV Devices
In either of the middle transceiver blocks.
In either of the two transceiver blocks.
In the middle transceiver block.
CMU Placement
Transceiver Channel Datapath Clocking
February 2011 Altera Corporation
Devices.
AN 578: Manual