EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 110

• Manufacturer Part Number: EP4SE530H35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 744
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

4–30
Stratix IV Device Handbook Volume 1
Shift Modes
1
1
Use the dynamic accum_sload control signal to clear the accumulation. A logic 1
value on the accum_sload signal synchronously loads the accumulator with the
multiplier result only, while a logic 0 enables accumulation by adding or subtracting
the output of the DSP block (accumulator feedback) to the output of the multiplier
and first-stage adder.
You must configure the control signal for the accumulator and subtractor if static at
compile time.
This mode supports the rounding and saturation logic unit because it is configured as
an 18-bit multiplier accumulator. You can use the pipeline registers and output
registers within the DSP block to increase the performance of the DSP block.
Stratix IV devices support the following shift modes for 32-bit input only:
■
■
■
■
■
You can switch between these modes using the dynamic rotate and shift control
signals.
You can use shift mode in a Stratix IV device by using a soft embedded processor such
as Nios
page 4–31
Shift mode makes use of the available multipliers to logically or arithmetically shift
left, right, or rotate the desired 32-bit data. You can configure the DSP block similar to
the independent 36-bit multiplier mode to perform shift mode operations.
Arithmetic shift right requires a signed input vector. During an arithmetic shift right,
the sign is extended to fill the MSB of the 32-bit vector. The logical shift right uses an
unsigned input vector. During a logical shift right, zeros are padded in the MSBs,
shifting the 32-bit vector to the right. The barrel shifter uses unsigned input vector
and implements a rotation function on a 32-bit word length.
Two control signals, rotate and shift_right, together with the signa and signb
signals, determine the shifting operation.
shift operations.
Arithmetic shift left, ASL[N]
Arithmetic shift right, ASR[32-N]
Logical shift left, LSL[N]
Logical shift right, LSR[32-N]
32-bit rotator or barrel shifter, ROT[N]
®
II to perform the dynamic shift and rotate operation.
shows the shift mode configuration.
Table 4–5 on page 4–31
Chapter 4: DSP Blocks in Stratix IV Devices
Stratix IV Operational Mode Descriptions
February 2011 Altera Corporation
Figure 4–20 on
lists examples of