EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 244

• Manufacturer Part Number: EP4SE530H35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 744
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

7–24
Figure 7–19. Number of DQS/DQ Groups per Bank in EP4S100G3, EP4S100G4, and EP4S100G5 Devices in the 1932-Pin
FineLine BGA Package
Notes to
(1) These numbers are preliminary until the devices are available.
(2) You can also use DQS/DQSn pins in some of the ×4 groups as R
(3) All I/O pin counts include dedicated clock inputs and dedicated corner PLL clock inputs that you can use for data inputs.
(4) You can also use some of the DQS/DQ pins in I/O Bank 1C as configuration pins. You cannot use a ×4 DQS/DQ group with any of its pin members
Stratix IV Device Handbook Volume 1
of the ×4 group are used as R
can use the ×16/×18 or ×32/×36 groups that include that ×4 group, however there are restrictions on using ×8/×9 groups that include that ×4
group.
used for configuration purposes. Ensure that the DQS/DQ groups that you have chosen are not also used for configuration because you may lose
up to four ×4 DQS/DQ groups, depending on your configuration scheme.
Figure
19 User I/Os
I/O Bank 2B
I/O Bank 1C
I/O Bank 2C
13 User I/Os
I/O Bank 1A
19 User I/Os
I/O Bank 2A
7–19:
40 User I/Os
x16/x18=0
x32/x36=0
x16/x18=0
x32/x36=0
39 User I/Os
x16/x18=0
x32/x36=0
x16/x18=0
x32/x36=0
x8/x9=0
x16/x18=0
x32/x36=0
x8/x9=0
x8/x9=0
x8/x9=1
DLL0
x8/x9=1
x4=0
DLL1
x4=1
x4=0
x4=3
x4=4
The DQS and DQSn pins are listed in the Stratix IV pin tables as DQSXY and DQSnXY,
respectively, where X indicates the DQS/DQ grouping number and Y indicates
whether the group is located on the top (T), bottom (B), left (L), or right (R) side of the
device. The DQS/DQ pin numbering is based on ×4 mode.
The corresponding DQ pins are marked as DQXY, where X indicates which DQS group
the pins belong to and Y indicates whether the group is located on the top (T), bottom
(B), left (L), or right (R) side of the device. For example, DQS1L indicates a DQS pin
located on the left side of the device. The DQ pins belonging to that group are shown
as DQ1L in the pin table. For more information, refer to
(Note
I/O Bank 8A
I/O Bank 3A
48 User I/Os
48 User I/Os
x16/x18=2
x32/x36=1
x16/x18=2
x32/x36=1
x8/x9=4
x8/x9=4
UP
x4=8
x4=8
1), (2), (3),
and R
DN
pins for OCT calibration. If two pins of a ×4 group are used as R
I/O Bank 8B
I/O Bank 3B
48 User I/Os
48 User I/Os
x16/x18=2
x32/x36=1
x16/x18=2
x32/x36=1
x8/x9=4
x8/x9=4
x4=8
x4=8
(4)
EP4S100G3, EP4S100G4, and EP4S100G5 Devices
I/O Bank 3C
I/O Bank 8C
32 User I/Os
32 User I/Os
x16/x18=0
x32/x36=0
x16/x18=0
x32/x36=0
in the 1932-Pin FineLine BGA
x8/x9=1
x8/x9=1
x4=3
x4=3
UP
and R
DN
I/O Bank 7C
32 User I/Os
I/O Bank 4C
32 User I/Os
x16/x18=0
x32/x36=0
x16/x18=0
x32/x36=0
x8/x9=1
x8/x9=1
pins, but you cannot use a ×4 group for memory interfaces if two pins
x4=3
x4=3
Chapter 7: External Memory Interfaces in Stratix IV Devices
I/O Bank 7B
I/O Bank 4B
48 User I/Os
48 User I/Os
x16/x18=2
x32/x36=1
x16/x18=2
x32/x36=1
x8/x9=4
x8/x9=4
x4=8
x4=8
Figure
I/O Bank 7A
I/O Bank 4A
48 User I/Os
48 User I/Os
x16/x18=2
x32/x36=1
x16/x18=2
x32/x36=1
x8/x9=4
x8/x9=4
UP
x4=8
x4=8
and R
February 2011 Altera Corporation
7–20.
Memory Interfaces Pin Support
DN
pins for OCT calibration, you
I/O Bank 6C
20 User I/Os
17 User I/Os
I/O Bank 6A
I/O Bank 5C
12 User I/Os
x16/x18=0
x32/x36=0
I/O Bank 5A
40 User I/Os
I/O Bank 5B
x16/x18=0
x32/x36=0
38 User I/Os
x16/x18=0
x32/x36=0
x16/x18=0
x32/x36=0
x8/x9=0
x16/x18=0
x32/x36=0
x8/x9=0
DLL3
x8/x9=0
x8/x9=1
x8/x9=0
x4=0
x4=0
x4=0
x4=4
DLL2
x4=3