EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 524

• Manufacturer Part Number: EP4SE530H35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 744
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

1–80
Figure 1–62. Rate Match FIFO Full Condition in PCIe Mode
Figure 1–63. Rate Match FIFO Empty Condition in PCIe Mode
Stratix IV Device Handbook Volume 2: Transceivers
pipestatus[2:0]
dataout
datain
1
pipestatus[2:0]
xxx
D1
D1
dataout
datain
Figure 1–62
FIFO becomes full after receiving data byte D4.
The rate match FIFO automatically inserts /K30.7/ (9'h1FE) after the data byte that
causes the FIFO to go empty and drives PCIestatus[2:0] = 3’b110 flag synchronous
to the inserted /K30.7/ (9'h1FE).
Figure 1–63
FIFO becomes empty after reading out data byte D3.
You can configure the rate match FIFO in low latency mode by turning off the Enable
Rate Match FIFO option in the ALTGX MegaWizard Plug-In Manager.
In XAUI mode, the rate match FIFO is capable of compensating for up to ±100 PPM
(200 PPM total) difference between the upstream transmitter and the local receiver
reference clock. The XAUI protocol requires the transmitter to send /R/ (/K28.0/)
code groups simultaneously on all four lanes (denoted as ||R|| column) during
inter-packet gaps, adhering to rules listed in the IEEE P802.3ae specification. The rate
match FIFO operation in XAUI mode is compliant to the IEEE P802.3ae specification.
The rate match operation begins after:
■
■
The rate match FIFO looks for the ||R|| column (simultaneous /R/ code group on
all four channels) and deletes or inserts the ||R|| column to prevent the rate match
FIFO from overflowing or under-running. It can insert or delete as many ||R||
columns as necessary to perform the rate match operation.
The synchronization state machine in the word aligner of all four channels
indicates synchronization was acquired by driving its rx_syncstatus signal high
The deskew FIFO block indicates alignment was acquired by driving the
rx_channelaligned signal high
Rate Match FIFO in XAUI Mode
xxx
D2
D2
shows the rate match FIFO full condition in PCIe mode. The rate match
shows rate match FIFO empty condition in PCIe mode. The rate match
D1
D1
xxx
D3
xxx
D3
xxx
D2
D2
D4
D4
xxx
3'b101
D6
D5
D3
D3
xxx
D6
D7
xxx
Chapter 1: Transceiver Architecture in Stratix IV Devices
/K30.7/
3'b110
D4
D8
D7
xxx
xxx
D4
D5
D8
xxx
February 2011 Altera Corporation
xx
Transceiver Block Architecture
xxx
D6
D5
xx
xx