EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 807

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EP4SE530H35C2N

Manufacturer Part Number
EP4SE530H35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
STRATIX® IV Er

Specifications of EP4SE530H35C2N

Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
744
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

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SIV52004-4.1
Stratix IV Device Handbook Volume 2: Transceivers
February 2011
February 2011
SIV52004-4.1
Stratix
clock multiplier unit (CMU) phase-locked loops (PLLs) independently. The ALTGX
Transceiver MegaWizard
each channel instantiated in your design. It also provides one power-down signal for
each transceiver block.
This chapter includes the following sections:
Figure 4–1
Figure 4–1. Reset Control and Power-Down Block
“User Reset and Power-Down Signals” on page 4–2
“Transceiver Reset Sequences” on page 4–4
“PMA Direct Drive Mode Reset Sequences” on page 4–24
“Dynamic Reconfiguration Reset Sequences” on page 4–36
“Power Down” on page 4–38
“Simulation Requirements” on page 4–39
“Reference Information” on page 4–39
®
IV devices offer multiple reset signals to control the transceiver channels and
shows the reset control and power-down block for a Stratix IV device.
gxb_powerdown
rx_analogreset
pll_powerdown
tx_digitalreset
rx_digitalreset
Plug-In Manager provides individual reset signals for
4. Reset Control and Power Down in
Reset Controller
Stratix IV Devices
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