EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 727

• Manufacturer Part Number: EP4SE530H35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 744
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 2: Transceiver Clocking in Stratix IV Devices
FPGA Fabric-Transceiver Interface Clocking
Figure 2–30. FPGA Fabric-Transmitter Interface Clocking in a x4 Bonded Channel Configuration
Note to
(1) The green lines represent the parallel PCS clock.
February 2011 Altera Corporation
Figure
2–30:
and Control
and Control
and Control
and Control
Channel 2
Channel 3
Channel 1
Channel 0
TX Data
TX Data
TX Data
TX Data
Logic
Logic
Logic
Logic
Bonded Channel Configuration
In ×4 and ×8 bonded channel configurations, all channels within the transceiver block
are identical. The Quartus II software automatically drives the write port of the
transmitter phase compensation FIFO in all channels with the coreclkout signal. Use
the coreclkout signal to clock the transmitter data and control logic for all four
channels in the FPGA fabric.
Figure 2–30
channel configuration.
FPGA
Fabric
tx_coreclk[1]
tx_coreclk[0]
tx_coreclk[2]
tx_coreclk[3]
shows the FPGA fabric-Transmitter interface clocking in a ×4 bonded
coreclkout
Reference
Clock
Input
/2
CMU0 PLL
CMU1 PLL
wrclk
wrclk
Compensation
wrclk
wrclk
Compensation
Compensation
Compensation
TX Phase
TX Phase
TX Phase
TX Phase
FIFO
FIFO
FIFO
FIFO
rdclk
rdclk
rdclk
rdclk
Divider
CMU0
Clock
/2
/2
/2
/2
Stratix IV Device Handbook Volume 2: Transceivers
Parallel PCS Clock
Parallel PCS Clock
Transmitter Channel PCS
Parallel PCS Clock
Parallel PCS Clock
Transmitter Channel PCS
Transmitter Channel PCS
Transmitter Channel PCS
CMU1 Channel
CMU0 Channel
Channel 2
Channel 3
Channel 0
Channel 1
(Note 1)
2–55