EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 629

• Manufacturer Part Number: EP4SE530H35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 744
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Figure 1–151. Synchronization State Machine in Serial RapidIO Mode
February 2011 Altera Corporation
1
1
Figure 1–151
implemented in Serial RapidIO functional mode.
Rate Match FIFO in Serial RapidIO Mode
In Serial RapidIO mode, the rate match FIFO is capable of compensating for up to
±100 PPM (200 PPM total) difference between the upstream transmitter and the local
receiver reference clock.
To enable the rate match FIFO in Serial RapidIO mode, the transceiver channel must
have both the transmitter and receiver channel instantiated. You must select the
Receiver and Transmitter option in the What is the operation mode? field in the
ALTGX MegaWizard Plug-In Manager. The 8B/10B encoder/decoder is always
enabled in Serial RapidIO mode.
Rate matcher is an optional block available for selection in SRIO functional mode.
However, this block is not fully compliant to the SRIO specification.
Data = !Valid
ecntr = 3
shows a conceptual view of the synchronization state machine
Synchronized Error
if Data == Comma
if Data == !Valid
Comma Detect
Loss of Sync
Synchronized
if gcntr==255
kcntr=kcntr
kcntr++
ecntr++
gcntr=0
gcntr=0
gcntr++
Detect
ecntr--
else
else
else
Data = Comma
kcntr = 127
Data = !Valid
Data=Valid
ecntr = 0
Stratix IV Device Handbook Volume 2: Transceivers
Data = valid;
kcntr < 127
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