EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 834

• Manufacturer Part Number: EP4SE530H35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 744
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

4–28
Figure 4–16. Reset Sequence with CDR in Automatic Lock Mode
Notes to
(1) For t
(2) For t
Stratix IV Device Handbook Volume 2: Transceivers
Reset and Power Down Signals
Figure
pll_powerdown
LTD_Auto
Ouput Status Signals
4–16:
duration, refer to the
rx_analogreset[0]
rx_analogreset[3]
pll_powerdown
rx_dataout[63:0]
rx_freqlocked[0]
rx_freqlocked[3]
duration, refer to the
pll_locked
Receiver and Transmitter Channel Set-up—Receiver CDR in Automatic Lock Mode
This configuration contains both a transmitter and receiver channel. For PMA Direct
drive ×N mode, with the receiver CDR in automatic lock mode, use the reset sequence
shown in
busy
DC and Switching Characteristics for Stratix IV Devices
1
t
pll_powerdown (1)
Figure
DC and Switching Characteristics for Stratix IV Devices
4–16. In this example, N = 4.
2
3
Minimum of Two Parallel Clock Cycles
4
5
5
Chapter 4: Reset Control and Power Down in Stratix IV Devices
chapter.
6
6
t
LTD_Auto (2)
chapter.
PMA Direct Drive Mode Reset Sequences
7
valid parallel data into FPGA fabric
February 2011 Altera Corporation